Napia

About

This is a virtual computing system I'm implementing to serve my needs going forward. It draws from my earlier systems (Maunga, Ngaro, Nga), adding in additional functionality and making adaptions to make it a tighter, more flexible system.

Architecture

Napia provides a 32-bit dual-stack processor, 64 KiB RAM / ROM, a block storage device, and basic I/O functionality. Memory is addressable as words, halfwords, and bytes. It supports signed and unsigned operations, relative calls and jumps. The processor provides 8 cores (operating in a round robin, cooperative manner), each with 24 words of internal register space and dedicated stacks. The address stack holds 128 values; the data stack holds 32.

Specification

The specification is still under development, but apart from I/O related parts is no longer changing significantly. (Some revisions to I/O are expected as development progresses; the final specification should be completed in the first half of 2022.)

Downloads

git clone https://git.sr.ht/~crc_/napia

RetroForth/Napia includes a copy of Napia. Get the Latest Snapshot (updated hourly) or git clone https://git.sr.ht/~crc_/retroforth-napia.

Other Resources

git clone https://git.sr.ht/~crc_/napia-rohi
an assembler for napia

git clone https://git.sr.ht/~crc_/napia-pl0
a PL/0 to napia assembly translator (in Python)

/r/napia on Reddit

Web Chat on IRC
  #retro on irc.libera.chat
  #retro:libera.chat (Matrix)
IRC Logs